An Implementation of a Grid Square Codes Generator on a RISC-V Processor

Abstract

This paper implements an execution unit that generates grid square codes from latitude and longitude on a RISC-V processor and evaluates its performance. In recent years, a statistical analysis which uses grid square codes has been focused. Although grid square codes are obtained from latitude and longitude based on several equations, this calculation requires a long computing time because it needs a lot of floating-point instructions.

In this paper, an execution unit which generates grid square codes from latitude and longitude is designed, and the instruction which generates grid square codes by using the unit is implemented on a RISC-V processor. The proposed execution unit can generate the corresponding grid square code from latitude and longitude in one cycle.

As a benchmark, a program that counts the number of times the randomly generated latitude and longitude match the specified grid square code is used. Experimental results show the in-order RISC-V processor with the proposed unit which implemented on an FPGA achieves a 36.6% reduction of execution time compared to the original processor. In addition, the performance evaluation of the out-of-order RISC-V processor with the proposed unit by using the gem5 simulator shows a 23.9% reduction of execution cycles compared to the original processor.

This paper also designs an execution unit which converts grid square codes to latitude and longitude. We call this conversion ”Grid-to-Degree conversion”. Experimental results show the in-order RISC-V processor with the unit which implemented on an FPGA achieves a 3.65% reduction of execution time compared to the original processor.