Evaluations of CMA with Error Corrector in Image Processing Circuit
To reduce power consumption, approximate computing is an efficient approach for error-tolerant applications such as image processing. Approximate arithmetic adders can be used for the approximate computing, and can trade off accuracy for power. CMA, a dynamically accuracy-configurable approximate adder, had been proposed. CMA can sharply reduce power consumption compared with other accuracy-configurable approximate adders, while allowing it to change accuracy-setting at run-time. In this paper, we evaluate CMA with error corrector that needs only two gates for each digit in actual image processing circuit. By increasing slight extra power, the proposed value corrector can improve PSNR quality of output images by up to 73.71%.
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