Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA

Abstract

This paper proposes a post-filtering system for improving the quality of depth maps for 3D projection on FPGA. We propose to implement the Weighted Least Square (WLS) filter on Field-programmable Gate Array (FPGA), which can predict the disparities, which cannot be measured, by using the values of the neighboring pixels. In our design, we optimized the architecture of WLS filter at the algorithm level. For hardware acceleration, we use the High-Level Synthesis (HLS) description to accelerate the algorithm. To break through the bottleneck brought by the limited memory resources on FPGA, we used UltraScale Architecture Memory Resources (URAM) on board and reduced memory consumption of Block RAMs (BRAM) from 140% to 80%. Through our approach, we can improve the quality of the depth map on the FPGA named M-KUBOS. And, the WLS filter can smooth the depth map with 130 MHz operational frequency on M-KUBOS at the speed of 10 frames per second (FPS), which achieves a 76.43% performance acceleration compared to the software execution on the ARM Cortex A9 at 1.2 GHz clock.